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PIC16FA-I/SP Technical Data
PIC usually pronounced as “pick” is a family of microcontrollers made by Darasheet Technologyderived from the PIC    originally developed by General Instrument ‘s Microelectronics Division. All current models use flash memory for program storage, and newer models allow the PIC to reprogram itself.
Program memory and data memory are separated. Data memory is 8-bit, bit, and, in latest models, bit wide. Program instructions vary in bit-count by family of PIC, and may be 12, 14, 16, or 24 bits long. The instruction set also varies by model, with more powerful chips adding instructions datasgeet digital signal processing functions.
Low-power and high-speed variations exist for many types. Third party and some open-source tools are also available. Some parts have in-circuit programming capability; low-cost development programmers are available as well as high-production programmers. PIC devices are popular with both industrial developers and hobbyists due to their low cost, wide availability, large user base, extensive collection of application notes, availability of low cost or free development tools, serial programming, and re-programmable Flash-memory capability.
InGeneral Instrument sold their microelectronics division and the new owners cancelled almost everything which by this time was mostly out-of-date. InMicrochip introduced Flash programmable devices, with full production commencing in Today, a huge variety of PICs are available with pic16f83 on-board peripherals serial communication modules, UARTsmotor control kernels, etc.
ByMicrochip was shipping over one billion PIC microcontrollers every year. PIC micro chips are designed with a Harvard architectureand are offered in various device families. The baseline and mid-range families use 8-bit wide data memory, and the high-end families use bit data memory.
The binary representations of the machine instructions vary by family datashfet are shown in PIC instruction listings. These devices feature a bit wide code memory, a byte register file, and a tiny two level deep call stack. Baseline devices are available in 6-pin to pin packages.
Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the remaining bytes are general purpose RAM. Pointers are implemented using a register pair: This affects register numbers 16—31; registers 0—15 are global and not affected by the bank select bits. The ROM address space is words 12 bits eachwhich may be extended to words by banking.
CALL and GOTO instructions specify the low 9 bits of the new code location; additional high-order bits are taken from the status register.
Note that a CALL instruction only includes 8 bits of address, and may only specify addresses in the first half of each word page. There are some “enhanced baseline” variants with interrupt support and a four-level call stack. PIC10F32x devices feature a mid-range bit wide code memory of or words, a byte SRAM register file, and an 8-level deep dstasheet stack. A complex set of interrupts are available.
These devices feature a bit wide code memory, and an improved 8-level deep call stack.
The instruction set differs very little from pic1f6873 baseline devices, but the two additional opcode bits allow registers and words of code to be directly addressed. There are a few additional miscellaneous instructions, and two additional 8-bit literal instructions, add and subtract.
The first 32 bytes of dataeheet register space are allocated to special-purpose registers; the remaining 96 bytes are used for general-purpose RAM. The 17 series never became popular and has been superseded by the PIC18 architecture however, see clones below. The 17 series is not recommended for new designs, and availability may be limited to users. Improvements over earlier cores are bit wide opcodes allowing many new instructionsand a level deep call stack. PIC17 devices were produced in packages from 40 catasheet 68 pins.
The 17 series introduced a number of important new features: A significant limitation was that RAM space was limited to bytes 26 bytes of special function registers, and bytes of general-purpose RAMwith awkward bank-switching in the models that supported more.
InMicrochip introduced the PIC18 architecture. In contrast to earlier devices, which were more often than not programmed in assembly, C has become the predominant development language. The 18 series inherits most of the features and instructions of the 17 series, while adding a number of important dwtasheet features:.
They are saved on every interrupt, and may be restored on return. Depending on which indirect file register is being accessed it is possible to postdecrement, postincrement, or preincrement FSR; or form the effective address by adding W to FSR.
In dtasheet advanced PIC18 devices, an “extended mode” is available which makes the addressing even more favorable to compiled code:.
InMicrochip introduced the pic16v873 series of chips,  which entered mass production in late They are Microchip’s first inherently bit microcontrollers.
PIC24 devices are designed as general purpose microcontrollers. Although still similar to earlier PIC architectures, there are significant enhancements: Instruction ROM is 24 bits wide. Software can access ROM in bit words, where even words hold the least significant 16 bits of each instruction, and odd words hold the most significant 8 bits.
The high half of odd words reads as zero. The program counter is 23 bits wide, but the least significant bit is always 0, so there are 22 modifiable bits. Instructions come in two main varieties, with most important operations add, xor, shifts, etc. The first is like the classic PIC instructions, with an operation between a specified f register i.
The W registers are memory-mapped. The second form is more conventional, allowing three operands, which may be any of 16 W registers. The destination and one of the sources also support addressing modes, allowing the operand to be in memory pointed to by a W register. There is no distinction between memory space and register space because the RAM serves the job of both memory and registers, and the RAM is usually just referred to as the register file or simply as the registers.
Special-purpose control registers for on-chip hardware resources are also mapped into the data space. The addressability of memory varies depending on device series, and all PIC devices have some banking mechanism to extend addressing to additional memory.
Later series of devices feature move instructions, which can cover the whole addressable space, independent of the selected bank. In earlier devices, any register move had to be achieved through the accumulator. External data memory is not directly addressable except in some PIC18 devices with high pin count.
In general, there is no provision for storing code in external memory due to the lack of an external memory interface.
All PICs handle and address data in 8-bit chunks. However, the unit of addressability of the code space is not generally the same as the data space.
In contrast, in the PIC18 series, the program memory is addressed in 8-bit increments byteswhich differs from the instruction width of 16 bits. In order to be clear, the program memory capacity is usually stated in number of single-word instructions, rather than in bytes.
PICs have a hardware call stackwhich is used to save return addresses. The hardware stack is not software-accessible on earlier devices, but this changed with the 18 series devices. Hardware support for a general-purpose parameter stack was lacking in early series, but this greatly improved in the 18 series, making the 18 series architecture more friendly to high-level language compilers.
The instruction set includes instructions to perform a variety of operations on registers directly, the accumulator and a literal constant or the accumulator and a registeras well as for conditional execution, and program branching.
Some operations, such as bit setting and testing, can be performed on any numbered register, but bi-operand arithmetic operations always involve W the accumulatorwriting the result back to either W or the other operand register. To load a constant, it is necessary to load it into W before it can be moved into another register.
On the older cores, all register moves needed to pass through W, but this changed on the “high-end” cores. PIC cores have skip instructions, which are used for conditional execution and branching. The skip instructions are “skip if bit set” and “skip if bit not set”.
Because cores before PIC18 had only unconditional branch instructions, conditional jumps are implemented by a conditional skip with the opposite pic16v873 followed by an unconditional branch. Skips are also of utility for conditional execution of any immediate single following instruction.
It is possible to skip instructions. The 18 series implemented shadow registers, registers which save several important registers during an interrupt, providing hardware support for automatically saving processor state when servicing interrupts.
The architectural decisions are directed at the maximization of speed-to-cost ratio. The PIC architecture was among the first scalar CPU designs [ citation needed ] and is still among the simplest and cheapest.
The Harvard architecture, in which instructions and data come from separate sources, simplifies timing and microcircuit design greatly, and this benefits clock speed, price, and power consumption. The PIC instruction set is suited to implementation of fast lookup tables in the program space. Such lookups take one instruction and two instruction cycles. Many functions can be modeled in this way. Optimization is facilitated pic61f873 the relatively large program space of the PIC e.
Interrupt latency is constant at three instruction cycles.
External interrupts have to be synchronized with the four-clock instruction cycle, otherwise there can be a one instruction cycle jitter. Internal interrupts are already synchronized. The constant interrupt latency allows PICs to achieve interrupt-driven low-jitter timing sequences. An example of this is a video sync pulse generator. This is no longer true in the newest PIC models, because they have a synchronous interrupt latency of three or four cycles.
The following stack limitations have been addressed in the PIC18 series, but still apply to earlier cores:. With paged program memory, there are two page sizes to worry about: This register must be changed every time control transfers between pages. Microchip will eventually phase out its older compilers, such as C18, and recommends using their XC series compilers for new designs. Judicious use of simple macros can increase the readability of PIC assembly language.